This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2001-386518, filed on Dec. 19, 2001; the entire contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same.
2. Related Background Art
Recently, as the miniaturization of semiconductor devices advances, gate widths of MOSFETs have become shorter, and the thicknesses of gate sidewalls composed of insulating layers and formed at side portions of gate electrodes have become thinner. In a semiconductor device having a MOSFET with a thin gate sidewall, a problem may arise that a deep diffusion layer constituting source/drain regions of the MOSFET tends to shift toward the gate electrode side. In order to avoid this problem, it is necessary to shallow the diffusion layer constituting source/drain regions.
Further, generally, a silicide layer is formed in source/drain regions in order to reduce parasitic resistance. In such a case, if the diffusion layer constituting the source/drain regions is caused to be shallow, the distance between the silicide layer bottom and the diffusion layer is shortened, thereby junction leakage current is increased. On the contrary, if the diffusion layer is caused to be deep, the short channel effect is deteriorated.
In order to avoid this, it is necessary to elevate or lift the diffusion layer. FIG. 15 shows the structure of an MOSFET having an elevated diffusion layer. In FIG. 15, an insulating layer 91 is formed on a semiconductor substrate or a well 90, and a gate electrode 92 of polycrystalline silicon is formed on the insulating layer 91. A gate sidewall 95 is formed at the side portion of the gate electrode 92. In the well immediately below the gate electrode 92, a channel region is formed, and at both the sides of the channel region in the well, a diffusion layer 94 serving as source and drain is formed. A shallow diffusion layer 93 (hereinafter also referred to as xe2x80x9cextension region 93xe2x80x9d) with a lower impurity concentration than the diffusion layer 94 is formed between the channel region and the diffusion layer 94. A silicon layer 96 is formed by epitaxial growth on the diffusion layer 94. Silicidation of the silicon layer 96 is then performed to form a silicide layer 97. With the MOSFET thus constituted, it is possible to inhibit the occurrence of junction leakage current even if miniaturization takes place. Accordingly, it is possible to prevent the degradation of short-channel effect.
However, there is a problem in making all the MOSFETs formed on a semiconductor substrate with an elevated structure. For example, in some circuit area, epitaxial growth may not be needed. Further, it may not be necessary to form all the MOSFETs with epitaxial layers having the same thickness.
For example, it is assumed that a logical circuit region and a DRAM (Dynamic Random Access Memory) region are mixedly formed on an SOI (Silicon On Insulator) substrate. In this case, a DRAM is formed in a DRAM forming area made by removing a portion of the SOI substrate, on which the DRAM is to be formed, together with the buried oxide layer, and by filing that portion with silicon; a number of logical circuits are formed on the SOI region without removing the buried oxide layer. Since there is a tendency to make thinner the thickness of silicon layer of an SOI substrate, on which a MOSFET is to be formed, to form a fully depleted MOSFET, it is necessary to form an epitaxial layer on a diffusion layer serving as source and drain in a MOSFET formed in an SOI region in order either to form a silicide layer on the diffusion layer or to reduce the sheet resistance of the diffusion layer under the silicide layer. On the other hand, however, it is not necessary to form an epitaxial layer by epitaxial growth in regions other than the SOI region (for example, a region in which the DRAM is formed). The reason for this is that if the optimization is not made in accordance with the thickness of epitaxial layer, junction capacitance may be increased, or parasitic resistance may be increased, thereby causing a problem that device characteristic or circuit performance is degraded.
Further, it is known that an n-channel MOSFET, which tends to form a rapid profile, does not need a thick epitaxial layer like a p-channel MOSFET. Since there is an optimum thickness of epitaxial layer for each type of MOSFET, if the thickness of epitaxial layer is uniformly set, the diffusion layer of one type of MOSFET is caused to be shallow, thereby increasing parasitic capacitance. Accordingly, a problem may arise that device characteristic and circuit performance are degraded.
A semiconductor device according to a first aspect of the present invention includes: a first MOSFET including: a first gate electrode formed on a first semiconductor layer in a first region of a semiconductor substrate; a first channel region formed immediately below the first gate electrode in the first semiconductor layer; a first diffusion layer constituting source/drain regions formed at both the sides of the first channel region in the first semiconductor layer; a first epitaxial layer formed on the first diffusion layer; and a first silicide layer formed on the first epitaxial layer; and a second MOSFET including: a second gate electrode formed on a second semiconductor layer in a second region of the semiconductor substrate; a second channel region formed immediately below the second gate electrode in the second semiconductor layer; a second diffusion layer constituting source/drain regions formed at both the sides of the second channel region in the second semiconductor layer; and a second silicide layer formed on the second diffusion layer.
A semiconductor device according to a second aspect of the present invention includes: a first MOSFET including: a first gate electrode formed on a first semiconductor layer in a first region of a semiconductor substrate; a first channel region formed immediately below the first gate electrode in the first semiconductor layer; a first diffusion layer constituting source/drain regions formed at both the sides of the first channel region in the first semiconductor layer; a first epitaxial layer formed on the first diffusion layer; and a first silicide layer formed on the first epitaxial layer; and a second MOSFET including: a second gate electrode formed on a second semiconductor layer in a second region of the semiconductor substrate; a second channel region formed immediately below the second gate electrode in the second semiconductor layer; a second diffusion layer constituting source/drain regions formed at both the sides of the second channel region in the second semiconductor layer; a second epitaxial layer, which is thinner than the first epitaxial layer, formed on said second diffusion layer; and a second silicide layer formed on the second epitaxial layer.
A method of manufacturing a semiconductor device according to a third aspect of the present invention includes: forming a first gate electrode on a first semiconductor layer in a first region of a semiconductor substrate, and a second gate electrode on a second semiconductor layer in a second region of the semiconductor substrate; forming a first diffusion layer in the first semiconductor layer using the first gate electrode as a mask, and a second diffusion layer in the second semiconductor layer using the second gate electrode as a mask; and selectively forming an epitaxial layer only on the first diffusion layer.